Three state current switch emitter follower gate circuits for providing a differential output state or an inhibit state under control of a select/deselect signal are well known in the art. The differential output state facilitates the employment of a differential bus in data processing equipment such as directory memory systems. The advantages of a differential bus over a single ended bus are to a significant degree offset by the increased power and delay of the differential output gate circuits of the prior art.
The tri-state current switch emitter follower gate circuit in accordance with the invention provides the advantages of differential bussing without incurring the power consuming penalty inherent in prior art differential output gate circuits.
In a directory memory system the use of gate circuits, in accordance with the invention, results in a differential data signal which eliminates read 0/read 1 skew and the problems inherent in generating a tracking reference.
As stated above, the present invention has particular utility and advantage when employed in a directory memory system for use in a data processing system having a cache memory, and more particularly to a directory memory system formed in a monolithic integrated circuit having the capability of performing simultaneous write/compare, read/compare, compare/bypass, write/bypass, or write/compare/bypass operations.
Directory memory systems, particularly directory memory systems fabricated in a single integrated circuit chip, have recently found increasing use in high-speed data processing systems. One example of such a directory memory system is described in U.S. Pat. No. 4,219,883 to Kobayashi et al. Such devices can be used advantageously to perform a number of different functions within the data processing system. One example is in a cache memory, which is a small, high-speed memory functionally positioned between a main, slower memory and a central processor. The cache memory stores the most frequently used data retrieved by the processor from the main memory for rapid access by the processor. Another application of a directory memory is in a "trace" system in which a predetermined amount of the data most recently used by the processor is stored for examination to locate possible faults within the data processing system. Many other applications, of course, are possible.
A directory memory system should generally have the capability of performing the functions of writing input data into a memory block for temporary storage therein, reading data from the memory block onto an output data bus, comparing designated portions of the data stored in the memory block with comparison data, and bypassing the comparison data onto the output data bus under certain conditions. The capabilities of directory memories are further enhanced by dividing the memory block array into two or more subarrays which are addressable either individually or in various combinations.
Directory memories which store and compare addresses associated with main and cache memories, and which have a memory array divided into two or more subarrays are well known. Typical systems are disclosed in U.S. Pat. Nos. 3,685,020 to Meade, 3,723,976 to Alvarez et al., 3,761,881 to Anderson et al., 4,044,338 to Wolf, 4,136,385 to Gannon et al., and 4,332,010 to Messina et al. Memory systems having two or more subarrays which are reconfigurable for write and/or read operations are disclosed in U.S. Pat. Nos. 3,686,640 to Andersen et al., 3,787,817 to Goldberg, 3,800,289 to Batcher, 3,958,222 to Messina et al., 4,087,853 to Kashio, 4,222,112 to Clemons et al., and 4,241,425 to Cenker et al. A memory having subarrays is also described in "Bit Line Constant Current Source Switch For A Read-Only-Store" by J. Perris et al., IBM TDB Vol. 20, No. 11A, April 1978, pp. 4412-4414.
Memory systems which have the capability of performing simultaneous operations have been disclosed. For example, systems which simultaneously write data into and read data from a memory array are described in U.S. Pat. Nos. 3,471,838 to Ricketts, Jr. et al., 3,761,898 to Pao, 4,070,657 to Fett, and in an article entitled "High-Speed Random-Access Memory With Simultaneous Read/Write Operation" by T. A. Williams, IBM TDB Vol. 17, No. 3, August 1974, pp. 933-934. Cache memories which perform a bypass function are disclosed in U.S. Pat. Nos. 4,075,686 to Calle et al. and 4,268,907 to Porter et al. A directory memory system including a simultaneous write and bypass function is disclosed in copending U.S. application Ser. No. 509,674, cited above, and a logic circuit having a bypass circuit therein is described in U.S. Pat. No. 4,286,173 to Oka et al.
Several prior directory memory systems are capable of performing simultaneous operations, however, these are limited to either compare, read/write, or write/bypass operations. This limited functionality is disadvantageous in that a greater number of memory or control cycles are required to complete the various operations. The overall processing speed of a data processing system is significantly increased by performing additional various combinations of operations simultaneously. A directory memory system having the capability of performing simultaneous write/compare read/compare, compare/bypass, write/bypass, or write/compare/bypass operations is disclosed and claimed in the above referenced related U.S. patent application Ser. No. 666,580 filed Oct. 30, 1984 and of common assignee herewith.